As the dimensions of features of semiconductor devices continue to be reduced, lithographic techniques and tools may need to be modified to accurately form functioning integrated circuit devices. Many techniques intended to adapt existing lithography tools to new fabrication demands, such as self-aligned double-patterning (SADP) processes, may involve multiple steps and patterning masks to form a finished integrated circuit layer according to a circuit design. In SADP processes, unidirectional lines are first formed, for example, by use of spacer process and a subsequent block mask step, using a block mask pattern, may be applied to form the line ends. SADP process may be implemented to manufacture a metal route layout. The route layout for metal line formation is often generated by automation tools following a set of predefined metal design rules. For the reason of routing efficiency, an EDA route tool often forms only metal line patterns and does not perform the block mask step. Consequently, the route layout may not successfully pass a block mask design rule check. Therefore, there is a need to develop a method of metal line design rule check that can ensure passing block mask design rule check.